Lithographic apparatus can be used, for example, in the manufacture of integrated circuits (ICs). In such a case, the mask may contain a circuit pattern corresponding to an individual layer of the IC, and this pattern can be imaged onto a target portion (e.g., comprising one or more dies) on a substrate (silicon wafer) that has been coated with a layer of radiation-sensitive material (resist). In general, a single wafer will contain a whole network of adjacent target portions that are successively irradiated via the projection system, one at a time. In one type of lithographic projection apparatus, each target portion is irradiated by exposing the entire mask pattern onto the target portion in one go; such an apparatus is commonly referred to as a wafer stepper. In an alternative apparatus, commonly referred to as a step-and-scan apparatus, each target portion is irradiated by progressively scanning the mask pattern under the projection beam in a given reference direction (the “scanning” direction) while synchronously scanning the substrate table parallel or anti-parallel to this direction. Since, in general, the projection system will have a magnification factor M (generally <1), the speed V at which the substrate table is scanned will be a factor M times that at which the mask table is scanned. More information with regard to lithographic devices as described herein can be gleaned, for example, from U.S. Pat. No. 6,046,792, incorporated herein by reference.
In a manufacturing process using a lithographic projection apparatus, a mask pattern is imaged onto a substrate that is at least partially covered by a layer of radiation-sensitive material (resist). Prior to this imaging step, the substrate may undergo various procedures, such as priming, resist coating and a soft bake. After exposure, the substrate may be subjected to other procedures, such as a post-exposure bake (PEB), development, a hard bake and measurement/inspection of the imaged features. This array of procedures is used as a basis to pattern an individual layer of a device, e.g., an IC. Such a patterned layer may then undergo various processes such as etching, ion-implantation (doping), metallization, oxidation, chemo-mechanical polishing, etc., all intended to finish off an individual layer. If several layers are required, then the whole procedure, or a variant thereof, will have to be repeated for each new layer. Eventually, an array of devices will be present on the substrate (wafer). These devices are then separated from one another by a technique such as dicing or sawing, whence the individual devices can be mounted on a carrier, connected to pins, etc. For the sake of simplicity, the projection system may hereinafter be referred to as the “lens”; however, this term should be broadly interpreted as encompassing various types of projection systems, including refractive optics, reflective optics, and catadioptric systems, for example. The radiation system may also include components operating according to any of these design types for directing, shaping or controlling the projection beam of radiation, and such components may also be referred to below, collectively or singularly, as a “lens.” Further, the lithographic apparatus may be of a type having two or more substrate tables (and/or two or more mask tables). In such “multiple stage” devices the additional tables may be used in parallel, or preparatory steps may be carried out on one or more tables while one or more other tables are being used for exposures. Twin stage lithographic apparatus are described, for example, in U.S. Pat. No. 5,969,441, incorporated herein by reference.
The photolithographic masks referred to above comprise geometric patterns corresponding to the circuit components to be integrated onto a silicon wafer. The patterns used to create such masks are generated utilizing CAD (computer-aided design) programs, this process often being referred to as EDA (electronic design automation). Most CAD programs follow a set of predetermined design rules in order to create functional masks. These rules are set by processing and design limitations. For example, design rules define the space tolerance between circuit devices (such as gates, capacitors, etc.) or interconnect lines, so as to ensure that the circuit devices or lines do not interact with one another in an undesirable way. The design rule limitations are typically referred to as “critical dimensions” (CD). A critical dimension of a circuit can be defined as the smallest width of a line or hole or the smallest space between two lines or two holes. Thus, the CD determines the overall size and density of the designed circuit.
Of course, one of the goals in integrated circuit fabrication is to faithfully reproduce the original circuit design on the wafer (via the mask). As the critical dimensions of the target patterns become increasingly smaller, it is becoming increasingly harder to reproduce the target patterns on the wafer. However, there are known techniques that allow for a reduction in the minimum CD that can be imaged or reproduced in a wafer. One such technique is the double exposure technique wherein features in the target pattern are imaged in two separate exposures.
For example, one commonly known double exposure technique is referred to as double-patterning or DPT. This technique allows the features of a given target pattern to be separated into two different masks and then imaged separately to form the desired pattern. Such a technique is typically utilized when the target features are spaced so closely together that it is not possible to image the individual features. In such a situation, the target features are separated into two masks such that all the features on a given mask are spaced sufficiently apart from one another so that each feature may be individually imaged. Then, by imaging both masks in a sequential manner (with the appropriate shielding), it is possible to obtain the target pattern having the densely spaced features that could not be properly imaged utilizing a single mask.
Thus, by separating the target features into two separate masks, such that the pitch between each of the features on a given mask is above the resolution capabilities of the imaging system, it is possible to improve imaging performance. Indeed, the above-mentioned double exposure techniques allow for a k1<0.25. However, problems and limitations still exist with currently known double exposure techniques.
For example, current decomposition techniques include rule-based decomposition techniques and model-based decomposition techniques. Rule-based methods typically require an excessive number of rules to handle today's increasingly complex designs. More specifically, with a set of pre-constructed geometric rules, it is possible to start performing pitch-split decomposition. This entails separating (also referred to as coloring) the odd and even pitch features into two separate geometry groups or patterns. Conceptually, this is straight forward process. However, in an actual IC circuit design, the local 2-dimensional geometry environment is very complex. As such, it is often difficult to identify “odd” and “even” pitch features from any of the localized dense pattern groups. As a result, the existing rule-based approach causes numerous coloring conflicts that need additional exceptional rules and/or operator intervention in order to resolve these conflicts. The need for such additional rules or operator invention make current rule-based systems very time consuming and problematic to utilize as often significant time must be taken to tailor the rule set to the given target design. Model-based decomposition processes also suffer from various disadvantages. For example, model-based decomposition methods can take an exceedingly long period of time to complete the decomposition process. Further, the model-based methods are also not immune from the non-resolvable conflict issues, and therefore can also require operator intervention, which is undesirable.
It is an object of the present invention to overcome such deficiencies in known rule-based and model-based pattern decomposition techniques.